This application claims priority from Korean Patent Application No. 2001-011133, filed on Mar. 5, 2001, the contents of which are herein incorporated by reference in their entirety.
The present invention relates to a nonvolatile memory device and, more particularly, to a method of sensing the data stored in a ferroelectric memory device including a memory cell comprising a ferroelectric capacitor and an access transistor.
A ferroelectric random access memory uses a ferroelectric capacitor to store memory cell data. Each memory cell stores a logic state based on electric polarization of the ferroelectric capacitor. The ferroelectric capacitor has a dielectric including a ferroelectric such as PZT (lead zirconate titanate) between two electrodes. When a voltage is applied to each plate of the ferroelectric capacitor, the ferroelectric is polarized in a field direction. A coercive voltage changes the polarization state of the ferroelectric capacitor. The ferroelectric capacitor operates with hysteresis, and current flows to the capacitor in accordance with the polarization state. If the applied voltage is greater than the coercive voltage, the ferroelectric capacitor will change the polarization state in accordance with a polarity of the applied voltage. The polarization state can be maintained after removing the power source, resulting in non-volatility. The ferroelectric capacitor changes between the polarization states within a short time, e.g., about 1 ns. The programming time of the ferroelectric memory device is faster than that of most other non-volatile memory devices such as erasable programmable read only memories (EPROMs), electrically erasable programmable read only memories (EEPROMs), and flash EEPROMs.
A conventional ferroelectric random access memory device is shown in FIG. 1. Referring to FIG. 1, the conventional ferroelectric random access memory device includes a memory cell array 10 comprising a plurality of ferroelectric memory cells, e.g. cells 11 and 12. The memory cell array 10 comprises a first ferroelectric memory cell M1 and a second ferroelectric memory cell M2. The first and second ferroelectric memory cells 11 and 12, respectively, each in turn comprise an access transistor (or pass transistor) and a ferroelectric capacitor
More specifically, in the first ferroelectric memory cell 11, an access transistor M1 has a gate connected to a first word line WL0. A current path exists between one electrode of the ferroelectric capacitor CF1 (referred to as a first internal cell node) and a first bit line BL0. The ferroelectric capacitor CF1 is connected between the first internal cell node and a plate line PL. In the second ferroelectric memory cell 12, an access transistor M2 has a gate connected to a second word line WL1. A current path exists between one electrode of the ferroelectric capacitor CF2 (referred to as a second internal cell node) and a second bit line BL1. The ferroelectric capacitor CF2 is connected between the second internal cell node and the plate line PL. Adjacent memory cells are arranged along other rows and share one plate line between them.
A reference voltage generator 20 is connected to the bit lines BL0 and BL1. The reference voltage generator 20 provides a reference voltage to either one of the bit lines BL0 or BL1. The reference voltage generator 20 comprises of three NMOS transistors MN1-MN3 and a reference capacitor RCF. Current paths of the NMOS transistors MN2 and MN3 are connected in series between the bit lines BL0 and BL1 and their gates are connected to corresponding control signals DMP0 and DMPE, respectively. The reference capacitor RCF is connected between a common node ND1 of the NMOS transistors MN2 and MN3 and a ground voltage. The NMOS transistor MN1 has a gate connected to a control signal DMPRS and a current path connected between a voltage line transmitting a reference voltage VREF and the common node ND1 of the NMOS transistors MN2 and MN3. In one embodiment, the reference capacitor RCF is a linear paraelectric capacitor.
FIG. 2 is a timing diagram of signals associated with the conventional ferroelectric random access memory device. A method for sensing data stored in the conventional ferroelectric random access memory device is as follows. First, word line, e.g. WL0, is activated to high level and the ferroelectric capacitor CF1 is connected to the bit line BL0 (to be referred to as main bit line hereinafter) through the access transistor M1 connected to the word line WL0. As the control signal DMPRS is pulsed, a predetermined reference voltage VREF is charged to the reference capacitor RCF of the reference voltage generator 20. By application of the pulse signal to the plate line PL, an electric field between the plate line PL and the main bit line BL0 is applied to the both electrodes of the ferroelectric capacitor CF1. As a result, a predetermined charge is excited in the main bit line in accordance with data (e.g. data xe2x80x981xe2x80x99) stored in the ferroelectric capacitor CF1. As the signal line DMPE is pulsed, the reference voltage VREF is transmitted to the bit line BL1 (to be referred to reference bit line hereinafter) through the NMOS transistor MN2. Since latch enable signals SAN and SAP are activated to a low and high level, respectively, a sense amplifier 30 detects a change of charge applied to the bit line BL0 by using the reference voltage supplied to the bit line BL1. As the detected result, a voltage of the main bit line BL0 goes to a power supply voltage Vcc level or a ground voltage GND level.
The method described above has a disadvantage. Since the loading capability of the main bit line BL0 is larger than that of the reference bit line BL1 at sensing time (when the latch enable signals SAN and SAP are activated), the data sensing margin (or a voltage difference between the main bit line and the reference bit line) is reduced. More specifically, before the latch enable signals SAN and SAP are transferred, the reference capacitor RCF is electrically insulated from the reference bit line BL1 of the reference voltage generator 20 by a high-to-low transition of the control signal DMPE. Before and after the latch enable signals SAN and SAP are transferred, while the reference bit line BL1 is insulated from the reference capacitor RCF, the main bit line BL0 is electrically connected to the ferroelectric capacitor CF1 of the memory cell. As shown in FIG. 3A, the reference bit line rises up more rapid than the main bit line. That is, when voltages of the main and the reference bit lines BL0 and BL1 attain the power supply voltage Vcc and the ground voltage GND (or ground voltage and power supply voltage), respectively, the data sensing margin is reduced. In the worst case, data xe2x80x981xe2x80x99 may be detected as data xe2x80x980xe2x80x99 because the voltage level of the main bit line BL0 is lower than that of the reference bit line BL1 as shown in FIG. 3B.
An object of the present invention is to overcome the disadvantages of the prior art.
Another object of the present invention is to provide a constant sensing margin when sensing data in a semiconductor memory device.
Yet another object of the present invention is to maintain equal the loading capability of a bit line with that of a complementary bit line when sensing data in a semiconductor memory device.
According to an aspect of the present invention, a ferroelectric random access memory device includes an access transistor having a gate connected to a word line and a current path connected between a bit line and internal cell node. A ferroelectric capacitor is connected between the internal cell node and a plate line. A reference voltage generator generates a reference voltage and includes a reference capacitor. Data is sensed in the ferroelectric capacitor by activating the word line so as to connect the ferroelectric capacitor to the bit line. After the plate line is activated, the reference capacitor is connected to a complementary bit line thereby developing a voltage difference between the bit line and the complementary bit line. The reference capacitor is insulated from the complementary bit line. The reference capacitor is equal or similar to that of the ferroelectric capacitor, and the reference of a linear paraelectric capacitor.
According to another aspect of the present invention, a ferroelectric memory device includes an access transistor having a gate connected to a word line and a current path connected between a bit line and an internal cell node. A ferroelectric capacitor is connected between the internal cell node and a plate line. A reference voltage generator for generating a reference voltage includes a reference capacitor. Data stored in the ferroelectric memory device is sensed by supplying the reference voltage to the reference capacitor, activating the word line so as to connect the ferroelectric capacitor to the bit line, activating the plate line, and simultaneously connecting the reference capacitor to the complementary bit line so as to supply the reference voltage. A sensing a voltage difference is sensed between the bit line and the complementary bit line. The reference capacitor is insulated from the complementary bit line. The word line is inactivated. The reference capacitor has a size equal or similar to that of the reference capacitor. The reference capacitor of a linear paraelectric capacitor.
According to yet another aspect of the present invention, a ferroelectric memory device includes a first memory cell having a first access transistor having a gate connected to a first word line and a current path connected between a bit line. A first ferroelectric capacitor is connected between the internal cell node and the plate line. A second memory cell having has a second access transistor with a gate connected to a second word line and a current path connected between a complementary bit line and internal cell node. A second ferroelectric capacitor is connected between the internal cell node and the plate line. A reference voltage generator for generating a reference voltage includes a reference capacitor. Data in the ferroelectric memory device is sensed by activating either one of the first or second word line so as to connect either one of the first or second ferroelectric capacitor to the bit line, activating the plate line and simultaneously connecting the reference capacitor to the complementary bit line. A voltage difference is sensed between the bit line and the complementary bit line and the reference capacitor is insulated from the complementary bit line.
According to yet another aspect of the present invention, a method for sensing data stored in the ferroelectric memory device is provided. The memory device includes a first memory cell having a first access transistor with a gate connected to a first word line and a current path connected between a bit line and an internal cell node. The device includes a first ferroelectric capacitor connected between the internal cell node and the plate line. A second memory cell has a second access transistor with a gate connected to a second word line and a current path connected between a complementary bit line and an internal cell node. A second ferroelectric capacitor is connected between the internal cell node and the plate line. A reference voltage generator for generating a reference voltage includes a reference capacitor. Data stored in the device is sensed by precharging the bit line and the complementary bit line, putting the bit line and the complementary bit line into floating states, activating either one of the first or second word line so as to connect either one of the first or second ferroelectric capacitor to the bit line, activating the plate line and simultaneously connecting the reference capacitor to a complementary bit line, sensing a voltage difference between the bit line and the complementary bit line, insulating the reference capacitor from the complementary bit line, and inactivating the activated word line. In one embodiment, the reference capacitor has a size equal or similar to that of the ferroelectric capacitor, and the reference capacitor is formed of a linear paraelectric capacitor.
Thus, before and after the sensing operation is carried out, the bit line has the same loading capability with a complementary bit line by electrically connecting a reference capacitor of the reference voltage generator to the complementary bit line.